From: DLA-E: a deep learning accelerator for endoscopic images classification
Refs. | Year | Architecture name | Main idea/Contribution |
---|---|---|---|
[24] | 2016 | ConvAU | A systolic array architecture based on Google’s TPU for accelerating massive matrix multiplication and accumulations |
[15] | 2017 | - | An FPGA accelerator for CNN inference utilizing parallelism |
[16] | 2017 | Escher | + CNN accelerator with flexible buffering to minimize off-chip transfer + Making balance between weight and input data transfer |
[17] | 2017 | - | Resource partitioning for different layers of CNN |
[25] | 2018 | CoNNA | + A reconfigurable coarse-grained FPGA CNN accelerator + Accelerating all layer types |
[18] | 2018 | AtomLayer | + CNN accelerator equipped with ReRAM + Handle CNN operations both in training and inference phases + Computation improvement in atomic layer |
[21] | 2018 | - | + High-performance depth wise CNN accelerator based on FPGA + Low power consumption and high speed for mobile devices |
[22] | 2019 | eCNN | + CNN accelerator for edge inference + Block based inference flow for removing all DRAM bandwidth related to feature maps reading |
[23] | 2020 | - | A reconfigurable FPGA-based CNN accelerator for YOLO network |
[26] | 2021 | SWM | + A CNN accelerator for inference phase + High performance accelerator using a dynamic scheduling strategy + Focusing on sparsity for reducing both memory and computation usage |
[27] | 2022 | MVP | A systolic array architecture for efficient processing of memory and computation intensive operations in CNNs like EicientNet and MobileNet |