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Journal of Big Data

Table 8 The performance model report, which has been calculated based on the bottlenecks like PCIe Rate, Computation time, Communication time, etc. Here the number of Super Logic Region (SLR) used is equal to 1

From: Distributed large-scale graph processing on FPGAs

Dataset

Partitions

SLRs

TFPGA (s)

Tbaseline (s)

Speedup

LiveJournal

16

1

1.92

12.86

6.7

Web-UK-2005

16

1

24.14

270

9.9

Twitter

16

1

37.3

538.1

7.2

Friendster

16

1

197.8

1340

12.6

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