Table 4 Formulas used in the baseline study

\(\text {P}=\left| \sqrt{\frac{S_{e}\times \left| E \right| }{S_{block}}} \right|\)

Total number of partitions based on GridGraph preprocessing

\(Size_{data} = S_{block} \times {P^2}\)

Edge block size to be processed

\(BW_{BRAM} = \frac{data_{width} \times {f_{FPGA}}}{S_{e}}\)

BRAM Bandwidth calculation

\(T_{mem} =\frac{\left| V \right| \cdot S_{v} + \left| E \right| \cdot S_{e}}{BW_{mem} \times {eff_{mem}}}\)

Load time for Vertex and Edges data from/to Global Memory to/from PE_FPGA

\(T_{PCIe} = \frac{size_{data}}{BW_{PCIe}\times {eff_{PCIe}}}\)

PCIe transfer time

\(T_{comm} = T_{init} + T_{PCIe} + T_{mem}\)

Transfer time from/to CPU host to/from PE_FPGA

\(T_{FPGA} = T_{comm} + T_{comp}\)

Total time for FPGA

\(T_{comp} = \frac{\left| V \right| + \left| E \right| }{BW_{BRAM}}\)

Computation time in the FPGA

\(S = \frac{S_{baseline}}{S_{FPGA}}\)

Speedup over the baseline execution time