Table 3 Baseline assumption and notations used in the baseline study
Symbol | Meaning | Con-stant value(if any) |
|---|---|---|
\(\left|V\right|\) | Number of vertices | Â |
\(\left|E\right|\) | Number of edges | Â |
Sv | Size of a vertex (Byte) | 4 |
Se | Size of an edge (Byte) | 8 |
datawidth | Depending on the scenario (1024, 2048, 4096) | 2048 |
\(P^{2}\) | The graph will be portioned into P\(\times\)P edge-blocks | Â |
Sblock | Size of an edge-block (MB) | 10 |
fFPGA | Clock Frequency MHz | 200 |
Tcomp | Time to process (read/Write to/from-chip BRAM) | Â |
Tcomm | Time to move data from host memory to FPGA | Â |
Tinit | Time to load the libraries (reduced after the first run) | Â |
TPCIe | Time to interconnect between boards | Â |
Tmem | Time to transfer data (loading blocks) between off-chip memory and PEs | Â |
Tbaseline | Time for CPU-only | Â |
TFPGA | Execution time in FPGA only | Â |
Sbram | BRAM storage size [it should be higher or equal to the size of each edge block Sbram ≥ Sblock(i,j)] (MB) | 54 |
BWmem | DDR4-2400 (GB/s) | 19.2 |
BWPCIe | PCIe 3.0 bandwidth ×16 (GB/s) | 32 |
effPCIe | PCIe efficiency | 0.8 |
effmem | Memory efficiency | 0.8 |
SL | Number of SLRs in the FPGA die | 4 |