Table 1 Brief overview of the closest recent studies on FPGA accelerators and their features compared to this work
Work | Distributed?a | Languageb | Implementationc | Access to host memoryd | Evaluation sizee | Public repository?f | FPGA platformg | Published yearh |
|---|---|---|---|---|---|---|---|---|
ForeGraph [19] | \(\checkmark\) | HDL | Simulation | \(\times\) | Medium | \(\times\) | Xilinx VCU110 | 2017 |
FabGraph [51] | \(\times\) | HLS | Simulation | \(\times\) | Medium | \(\times\) | Xilinx VCU110 and VCU118 | 2019 |
HitGraph [70] | \(\times\) | HDL | Hardware | \(\times\) | Small | \(\checkmark\) | Xilinx Virtex Ultrascale+ | 2019 |
ThunderGP [16] | \(\times\) | HLS/C++ | Hardware | \(\times\) | Medium | \(\checkmark\) | Alveo Family | 2021 |
GraVF-M [24] | \(\checkmark\) | Pythonii | Hardware | \(\checkmark\) | Medium | \(\checkmark\) | Micron Pico se-6 platform | 2019 |
GridGAS [74] | \(\checkmark\) | HDL | Hardware | \(\checkmark\) | Medium | \(\times\) | Xilinx Kintex | 2018 |
FPGP [18] | \(\times\) | HDL | Hardware | \(\times\) | Medium | \(\times\) | Xilinx Virtex-7 | 2016 |
FDGLib [60] | \(\checkmark\) | HDL/C++ | Hardware | \(\times\) | Small | \(\times\) | Alveo Family | 2021 |
Asitatici and Ienne [6] | \(\times\) | Chisel | Hardware | \(\times\) | Large | \(\checkmark\) | Xilinx Virtex Ultrascale+ (AWS Platform) | 2021 |
GraphOps [46] | \(\times\) | MAXJ | Hardware | \(\times\) | Small | \(\times\) | MAXELER Boards | 2016 |
This Work | \(\checkmark\) | HLS/C++ | Hardware | \(\checkmark\) | Very Large | \(\checkmark\)j | Alveo Family | 2022 |